Job Description
| Staff Systems Engineer, IP The successful candidate… Will develop high performance IP designs beyond the capabilities of FPGAs Will author both internal and customer documents Will maintain revisions and release process Will help bring up IP in the lab Will work with HW, systems, architecture, SW and AE teams on a daily basis Requirements: Strong HDL experience, Verilog preferred Strong timing closure experience in ASIC or FPGA flows, FPGA preferred Strong lab experience for design bring up Excellent communication skills Preferred Skills: High speed serial IO protocols High performance networking applications Good understanding of revision control concepts, specific tool is not important Good verbal communication skills, teamwork Years Experience: 5-10 Education Requirements: BS or MS This is a unique opportunity to join a team of industry leading innovators and bring to life a product that achieves never heard of performance levels for a programmable product. The successful candidate will work with leading IP providers and product architecture/design teams of leading companies in the high speed communications and high performance computing industries. *No Agencies Please. |
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